PACT: G: Towards Effective Parallelization and Accelerator Offloading for Heterogeneous Multicore Embedded Systems

The use of Multiprocessor Systems on Chip (MPSoCs) is a common practice in the design of state-of-the-art embedded devices, as they provide a good performance, energy and cost trade-off. However, MPSoC programming is still an error-prone and time consuming task that currently involves several manual steps. This task becomes even more challenging for heterogeneous architectures, where general purpose processors are combined with accelerators. In this work, we describe an approach that jointly addresses extraction of multiple parallel patterns and accelerator offloading from sequential applications targeting heterogeneous MPSoCs. Results show the effectiveness of our approach, as we are able to speedup sequential benchmarks significantly on two commercial platforms.